Double gate MOS devices have drawn increasing interest within the recent years because of their capability to reduce short channel effects. The downscaling of MOS devices will continue for the next decade. By this downscaling, the physical limitations of device behavior, as predicted for planar devices, are reached and partially exceeded. Thus, the so-called short channel effects become an issue, which is answered by the changing of device layout. For sub 50 nm devices, the double gate device layout is one of the most promising concepts to deal with the issue of short channel effects. Therefore, double gate devices have drawn increasing attention recent years. In double gate devices, there are two gates biased in parallel to form an inversion channel on both sides of a silicon layer. If the silicon layer is thin enough, these two inversion channels will overlap. The field penetration from drain to source is decreased, which decreases short channel effects.
There are three different layouts of double-gate MOS devices. In the first layout, the channel and the current are in the plane of the wafer, so one gate is above and one gate is below the channel layer. The second layout is the so-called FinFET layout. The silicon channel layer is perpendicular to the wafer surface, but the current is still in the plane of the wafer. The third layout, like the FinFET, has a silicon ridge of a few tenths of nanometers in thickness, which is the active area of the transistor. In this layout, the current flow is perpendicular to the surface of the wafer.
FIG. 1 illustrates a conventional double gate device 1 having the first layout with one gate above another. It comprises source and drain 8, a top gate 2, a bottom gate 4 and a channel 6. The channel 6 resides between the top gate 2 and the bottom gate 4, and is typically separated by oxides 3. The double gate device 1 needs a complex process flow, including epitaxy, to produce the double gate structure. In one of the conventional methods, the buried oxide 3 is formed first. A cavity is then formed for the channel 6 and source and drain regions 8. The channel 6 and source and drain regions 8 are then epitaxially grown from a seed silicon. The conventional double gate devices and forming methods have some disadvantages. The forming methods are complex and costly. Channel thickness T is typically in the range of about 10 nm so that it is hard to use the conventional methods to achieve desired threshold voltage. The conventional double gate devices could become inactive when the bottom gate voltage is high, such as around 2.5V. This significantly limits the performance improvement.
Double gate devices can be used for different applications by adjusting bottom gate voltage. Typically, when high performance is desired, a higher bottom gate voltage can be applied so that the device has higher speed, although the sub-threshold leakage and power consumption are high. When low power is desired, for example, when a circuit is in standby mode, a lower bottom gate voltage can be applied. With a low bottom gate voltage, the leakage current and power consumption are significantly lower. However, the circuit speed is lower.
The double gate device will become a mainstream technology in the semiconductor technology because of its superior device behavior during scaling. The present invention proposes a new device structure and process forming the double gate device.